Static Timing Analysis (STA) is a key step in the design of high speed Very Large Scale Integrated (VLSI) circuits. It is used to verify that a given VLSI circuit design performs correctly at a required frequency before it is released to manufacturing. STA is performed on a timing graph representation of the design; the points in the design where timing information is desired constitute the nodes or timing points of the graph, while electrical or logic connections between nodes are represented by timing arcs of the graph. STA typically consists of certain fundamental steps that include:                i. delay calculations, which involves modeling and calculating delays across the gates and interconnects (represented by timing arcs) included in the timing graph representation of the design;        ii. propagation and calculation of signal arrival times, required arrival times and slews across all timing points, and        iii. slack calculation across all timing points of the design.        
With modern chip manufacturing technology scaling to sub-65 nanometers, VLSI designs are increasingly getting larger in terms of size and complexity. Design-architecture, analysis and/or optimization of any such large design is immensely complex, and often prohibitive. For example, timing optimization of a flattened microprocessor design would be practically impossible by any Computer-Aided Design tool from a tool run-time and memory consumption perspective. Given the numerous iterations that a design optimization flow requires, a flattened view of a design also prohibits parallel design-architecture and optimization efforts. These challenges coupled with aggressive time-to-market schedules have led to a hierarchical design view, analysis and optimization flow for modern VLSI designs. A high level design partitioning is performed to create the hierarchy. Partitioning may be performed recursively within a level of hierarchy to create a global multi-level hierarchy of the chip design.
In hierarchical timing, the partition of the design at a given level of hierarchy is analyzed in isolation. This facilitates analysis and/or optimization of different partitions of the design in parallel. In the context of timing verification, detailed (accurate, using complex timing models or circuit simulation engines) static timing analysis of a partition is followed by the generation of timing abstract models that reflect in a simpler form, the actual timing characteristic of the partition being analyzed. The latter step is termed timing abstraction. For ease of notation, hereinafter, the term macro will be used to denote any circuit partition being abstracted, irrespective of the global level of hierarchy. A macro may represent a transistor level design, consisting of Field Effect Transistor (FET) devices and interconnects, or a gate level design, consisting of gates and interconnects. Inputs and outputs of the macro are denoted as macro primary inputs (PIs) and macro primary outputs (POs), respectively.
A generated abstract captures the timing characteristic of the macro using slew and load dependent tables to model the timing behavior of the logic. The abstract model is required to be context-independent, that is, independent of the voltage waveforms (slews) at its primary inputs and loads at its primary outputs. Consequently, delays and output slews (or waveforms) of timing arcs near the primary inputs of the macro are characterized as functions of input slew, while delays and output-slews of arcs closer to the macro primary outputs are characterized as a function of output load, and sometimes a combination of both. This allows the generated abstract models to be used in multiple boundary condition (PI and PO) settings. Timing abstraction employs techniques directed to reducing the size of the timing graph by performing pruning as well as arc compression. These techniques can reduce significantly the number of timing arcs to be timed at the next level of hierarchy. The abstract model essentially represents the macro as a complex gate, and obfuscates the internal details of the circuit. This may be desirable for generating designs shared between vendors, and provides motivation for generation of abstracts as industry standard gate models.
Referring to FIG. 1, an illustrative macro 100 is shown having a macro primary input port 101 and a macro primary output port 109. An interconnect 102 (also referred to as a net) connects the primary input to gate 104. Gate 104 feeds logic 105 that includes other gates and nets, and finally connects to gate 106. Net 107 connects gate 106 to the macro primary output 109. The resistance-capacitance (RC) parasitics of the interconnect segment 102 are referenced by numeral 103, while the RC parasitics of the interconnect segment 107 are referenced by numeral 108. The timing abstract model of the macro is shown as block 110. The macro primary input port 101 and macro primary output port 109 are preserved in the abstract model as 111 and 113, respectively. However, the internal segments and components of the macro (e.g., 102 and 104) are abstracted and may even be merged. Block 110 is considered as a complex gate that no longer includes interconnects. The timing arcs in the abstract model are characterized some as functions of input slew, or output load or both, and the timing model is stored preferably in a standard industry format (e.g., lib© format). To capture the load seen from the primary input, the total capacitive load of the interconnect segment 102 and the input pin capacitance of gate 104 are summed and set as the lumped pin capacitance 112 on the input port 111 of the abstract model. The load seen from the macro PI may also be captured as a slew dependent pin capacitance as described in co-pending U.S. patent application Ser. No. 12/426,492 of the same assignee. This avoids approximating the parasitics 103 of interconnect segment 102 as a lumped capacitance, thereby helping to improve the accuracy of the STA at the next (upper) level of hierarchy.
Pin capacitances are preferably stored only for the macros' PIs of the abstract. This is because any logic feeding (or driving) the abstract model at an upper level of hierarchy requires only the load seen from the PI of the macro during timing analysis of the logic. Since all the internal interconnect segments (that are not directly connected to a primary input) in a given macro are characterized (for delay and output waveform/slews), and are not fed by any external logic during hierarchical timing, their respective parasitics information is not stored. For illustrative purposes, in prior art FIG. 1, the delay and output waveform/slew across interconnect segment 102 is accurately characterized as a function of different voltage waveforms (i.e., a range of input slews) at the macro PI during abstraction. Characterization takes into account detailed parasitics 105 of the interconnect segment, and is thus accurate. Interconnect segments that are connected to the macro POs and gate segments feeding the macro interconnect segments are both characterized (as functions of input waveform/slew and load at macro primary output), accurately taking into account the detailed interconnect parasitics. Since no external logic is expected to feed the segments directly during hierarchical timing, a lumped pin capacitance capturing the parasitics for these interconnect segments is typically not required. Consequently, the RC parasitics of the interconnect segments connected to the macro PIs (e.g., segment 108 in macro 100, FIG. 1) are not captured in the abstract.
At the next (upper) level of hierarchy (referenced as chip level, for ease of notation), macros are represented by their corresponding abstracts. The term chip level is generically applied to denote a level of hierarchy where an abstract generated at a lower level of hierarchy is included for STA.
Referring now to FIG. 2, a hierarchical design 200 is shown at the chip level of hierarchy that includes multiple abstracted macros. One abstracted macro within this chip level of hierarchy is labeled 201. Each macro internal to block 200 is not necessarily unique. Multiple instances of a particular macro may exist at upper levels of the hierarchy. These are modeled using multiple instances of the abstract corresponding to a particular macro. Global wires and gates (termed glue-logic, e.g., 202) are connected to one or more macros within the chip level, as well as to the PIs and Pos at the chip level. Each unique macro is separately timed and abstracted and, subsequently, the abstract model is used to denote its timing model during hierarchical chip-level STA.
The hierarchical timing approach enables fast timing analysis and enhances the productivity at the chip level since the abstract models are simple table-lookup models (that facilitate a fast delay and/or slew computation) and allow re-use. These benefits are significantly highlighted when multiple instances of a macro appear at the chip level since the flow avoids expensive separate static timing analysis for each instance of the macro by limiting accurate STA and abstraction only once per unique macro.
Although abstraction provides significant productivity improvements at chip level timing, the conversion of a complex macro containing interconnect segments and gates to an abstract gate model poses potential timing accuracy issues in certain situations. For example, if the interconnect segment connected to a macro PI is highly resistive and the parasitics of this segment is captured as a lumped pin capacitance in the abstract PI, a gate driving this abstract at the chip level will incur inaccuracies during delay and output slew calculation, since it sees a lumped load instead of detailed RC parasitics. Co-pending U.S. patent application Ser. No. 12/426,492 describes a method to overcome this problem by capturing interconnect RC parasitics as a slew dependent pin capacitance on the PI of the abstract. A similar problem exists when an interconnect segment connected to a macro PO is resistive. This problem is, however, not addressed by the above invention.